A nitride-based semiconductor, such as GaN, AlGaN, InGaN, InAlN, or InAlGaN, has high dielectric breakdown strength, high thermal conductivity, and a high saturated electron velocity. Therefore, the nitride-based semiconductor is preferable as a semiconductor material used to manufacture a power device for power control, such as a high frequency device or a switching element. In recent years, a technique for putting a field effect transistor using a nitride-based semiconductor material into practical use has been actively developed.
It is preferable that the field effect transistor using the nitride-based semiconductor as a semiconductor material be a normally-off (enhancement) type which does not require a negative DC bias power supply for supplying power to the gate electrode of the field effect transistor. For example, a normally-off (enhancement) field effect transistor using a nitride-based semiconductor material shown in FIG. 12 has been proposed (for example, Patent Document 1).
FIG. 12 shows the structure of the normally-off (enhancement) field effect transistor using the nitride-based semiconductor material which is disclosed in Patent Document 1. Next, the normally-off field effect transistor using the nitride-based semiconductor disclosed in Patent Document 1 will be described with reference to FIG. 12.
The field effect transistor shown in FIG. 12 has a structure in which a carrier travel layer 1 made of AlXGa1-XN (0≦X<1), which is an undoped nitride semiconductor, a barrier layer 2 made of AlYGa1-YN (0<Y≦1 and X<Y), which is an undoped or n-type nitride-based semiconductor having a lattice constant smaller than that of the carrier travel layer 1, a threshold value control layer 3 that is made of an undoped or n-type semiconductor having the same lattice constant as that of the carrier travel layer 1, and a carrier inducing layer 4 made of InWAlZGa1-W-ZN (0<W≦1 and 0<Z<1) are sequentially laminated. In addition, a recess structure 30 in which the entire carrier inducing layer 4 and a portion of the threshold value control layer 3 are removed is formed at a position where the gate electrode 5 is formed. Then, a gate electrode 5 is formed so as to cover the recess structure 30. A source electrode 6 and a drain electrode 7 are substantially symmetrically formed on the carrier inducing layer 4 with the gate electrode 5 interposed therebetween.
In Patent Document 1, in the field effect transistor shown in FIG. 12, the barrier layer 2 is formed to have a thickness d1 represented by the following Expression 1, thereby achieving a normally-off field effect transistor:d1≦16.4×(1−1.27×(Y−X))/(Y−X)[Å]  [Expression 1]
(where Y−X<1/1.27 is satisfied).
In Patent Document 1, in the transistor shown in FIG. 12, the gate electrode 5 is formed in the recess structure 30 having a bottom in the threshold value control layer 3. However, since the threshold value control layer 3 is made of a semiconductor material having the same lattice constant as that of the carrier travel layer 1, the threshold voltage (Vt) of the transistor does not vary depending on the thickness of the threshold value control layer 3. That is, even when there is a variation in etching depth during the formation of the recess structure 30, it is possible to reduce a variation in the threshold voltage of the transistor since the threshold voltage does not vary.